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LT3743
PIN FUNCTIONS
(QFN/TSSOP)
PWMGL (Pin 22/Pin 23): The PWMGL output pin drives
the gate of an external FET to connect one of the switching
regulator output capacitors to the load. The driver pull-up
impedance is 3.2Ω and pull-down impedance is 1.75Ω.
HG (Pin 23/Pin 24): HG is the top FET gate drive signal
that controls the state of the high side external power
FET. The driver pull-up impedance is 2.3Ω and pull-down
impedance is 1.3Ω.
SW (Pin 24/Pin 25): The SW pin is used internally as the
lower rail for the floating high side driver. Externally, this
node connects the two power FETs and the inductor.
LG (Pin 26/Pin 28): LG is the bottom FET gate drive sig-
nal that controls the state of the low side external power
FET. The driver pull-up impedance is 2.5Ω and pull-down
impedance is 1.3Ω.
V CC_INT (Pin 27/Pin 1): A regulated 5V output for charging
the C BOOT capacitor. V CC_INT also provides the power for
the digital and switching subcircuits. Below 6V V IN , tie
this pin to the rail. V CC_INT is current limited to ≈50mA.
Shutdown operation disables the output voltage drive.
V IN (Pin 28/Pin 3): Input Supply Pin. Must be locally
bypassed with a 1μF low ESR capacitor to ground.
CBOOT (Pin 25/Pin 26): The CBOOT pin provides a
floating 5V regulated supply for the high side FET driver.
An external Schottky diode is required from the V CC_INT
pin to the CBOOT pin to charge the C BOOT capacitor when
the switch pin is near ground.
3743fd
10
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